Did you mean the main University group (s) that defined and implemented the ISA? If so, I agree they've done well. I especially loved that they open-sourced a 1+GHz 48nm core. Awesome stuff.
I posted a link to Schneiers Squid thread today on a bunch of asynchronous chip work. One was a 180nm FPGA w/ several times Xilinx's performance and one a 40nm microcontroller. I imagine a combination of RISC-V with that async flow would produce one drool-worthy processor in price, performance, and NRE cost.
Yeah...that 1GHz core could be the game changer as far as Open Source hardware goes. Seems pretty much anyone with an above average undergrad digital design competency has cooked up a core/ISA that ranges from the few tens to a few hundred MHz, but a real 1GHz core on a real process potentially puts it in range of the ARM/MIPS crowd performance wise (that is, out of "isn't that a cute toy" territory).
I confess to not being particularly conversant with async design (it became mainstream after my time), but I'll definitely check out your links and see what I can learn.
You're welcome. I have over ten thousand in all and someone just asked me for dome on making C programs memory safe. So if you like that too check back on my profile's comments in a day or so.
I posted a link to Schneiers Squid thread today on a bunch of asynchronous chip work. One was a 180nm FPGA w/ several times Xilinx's performance and one a 40nm microcontroller. I imagine a combination of RISC-V with that async flow would produce one drool-worthy processor in price, performance, and NRE cost.