That said AVH-lite is called lite because it is a simplified form of the arm norm.
The RP2350 can issue one fetch and one load/store per cycle, and that is that almost everything called a CPU and not a MCU will have ABH5 or better.
The “von Neumann bottleneck” was (when I went to school) that the CPU cannot simultaneously fetch an instruction and read/write data from or to memory.
That doesn’t apply to smartphones, PCs or servers even in the intel world due to instruction caches etc…
> That said AVH-lite is called lite because it is a simplified form of the arm norm.
> The RP2350 can issue one fetch and one load/store per cycle, and that is that almost everything called a CPU and not a MCU will have ABH5 or better.
I mean, yes, but I'm not sure I see your point. The Harvard vs Von Neumann architectural difference is more related to the number of AHB ports on the core.
> That doesn’t apply to smartphones, PCs or servers even in the intel world due to instruction caches etc…
I wouldn't confuse instruction caches with Harvard vs Von Neumann either - loads of Von Neumann machines have instruction or Flash caches too.
It's also not uncommon to run into Von Neumann cores in mobile and PC chips, just as peripheral co-processors.
It is just middle aged guy who did this stuff for years...
That said AVH-lite is called lite because it is a simplified form of the arm norm.
The RP2350 can issue one fetch and one load/store per cycle, and that is that almost everything called a CPU and not a MCU will have ABH5 or better.
The “von Neumann bottleneck” was (when I went to school) that the CPU cannot simultaneously fetch an instruction and read/write data from or to memory.
That doesn’t apply to smartphones, PCs or servers even in the intel world due to instruction caches etc…
It is just old man yells at clouds