> There is NO opportunity for large scale integration
What about vertically?
CMOS logic is still "mostly planar". With sufficiently low heat dissipation, you could make a cube and easily overcome the planar density problem.
The main challenge seems like it would be lithography cost for each of the many layers, but if the minimum feature size is 1.5um, there might be a clever way to make this work cheaply (DLP projection + gradual extrusion?)
What about vertically?
CMOS logic is still "mostly planar". With sufficiently low heat dissipation, you could make a cube and easily overcome the planar density problem.
The main challenge seems like it would be lithography cost for each of the many layers, but if the minimum feature size is 1.5um, there might be a clever way to make this work cheaply (DLP projection + gradual extrusion?)