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I think this may be a bit too many instructions (I did not see hardware accelerated memcpy/memset though). I guess I would use only a small subset of them. Since RISC-V is a royalty free standard, writting directly assembly is worth it, until the abuse of a macro processor and code generation is avoided.

I want to share you optimism, but I advise you to keep your cool. There is a long road to reach the performance of x86/arm microarchitectures (it is harder for risc-v since the "market is over saturated"). And those performant implementations must get access to the best silicium node process... and that...



Veyron and Ascalon's planned releases aren't "IP to license" releases, but actual chips.

Veyron's supposed to have actual server boards on sale late this year.

Ascalon, CPU chiplets and a full AI accelerator product using them, succeeding their current one, which iirc uses SiFive IP.




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