Chips themselves aren't actually very regular in terms of their layout -- not all tracks are connected the same way, parts are partitioned across different clocking areas, some parts of the chip contain things like memory resources while others do not, etc. You don't actually have a perfectly symmetrical die. FPGAs for example are quite "heterogenous" in the device resources they contain (clocks, DSPs, memory, registers) and they are scattered in many places over the chip. (Note that FPGA resources are fixed while ASIC layouts are not, but both of them use simulated annealing/analytic placement algorithms in the design phase for automatically laying out digital logic among the chip. Both of these problems, while complex, do ultimately aim to solve the optimization problem of minimizing wire-length -- among many other timing/clocking constraints.)